The invention relates to a digital DPCM-coder having a high processing speed, with a quantizer from whose output quantized DPCM-signals are emitted. A calculating loop serves to determine an estimated value. The loop contains an adder and a multiplier in which multiplication by a prediction factor takes place, and a subtractor which precedes the input of the quantizer and whose first input is supplied with a PCM signal and whose second input is supplied with the estimated value.
FIG. 1 of the drawings illustrates a known DPCM-coder which determines the DPCM-signal in four calculating steps. The function thereof will be explained in further detail later in the description. At high transmission speeds the known construction of the DPCM-coder necessitates excessively long calculation times even when modern circuit technology is used.